The present invention relates to ring oscillators, and, more particularly, to a low power ring oscillator having a extra low jitter.
The ring oscillator is a common building block in most communication systems, especially in such applications as phase locked loops, clock generators and clock distribution systems. An advantage for ring oscillators is that they can be integrated on a chip without external components which is essential in architectures where space is a premium. Important characteristics of a ring oscillator include frequency of operation, jitter, phase noise, tuning range, supply voltage variation, and frequency stability with respect to temperature.
FIG. 1 illustrates a known differential structure which is the preferred conventional approach to reduce the effects of noise and interference on the chip. It is comprised of several cascaded stages of identical differential delay cells, D1, D2, and D3 coupled to PMOS transistors MP1, MP2 and MP3. FIG. 2 displays a known differential delay cell including PMOS transistors MP4 and MP5 and NMOS transistors MN1, MN2, MN3 and MN4 coupled to form the differential structure.
A common problem of a CMOS ring oscillators, however, is that of a lower phase noise performance when compared to a LC oscillator or a crystal oscillator. Particularly, in low power applications, the amount of jitter in a ring oscillator is determined by the nature of the differential delay cells and the biasing tail currents. In an effort to reduce the overall jitter of a ring oscillator, care must be taken to ensure that each differential delay cell contributes minimal jitter. Furthermore, in extra low power applications on the order of several tens of microamps, the device noise of each tail current transistor is also an significant source of jitter.
A conventional approach for further reducing jitter or phase noise of the differential oscillators is to increase the current supplied to the differential oscillator. However, due to the low power design, the supply current is limited.
There, however, exists a need for a low power ring oscillator having extraordinarily low jitter.
To address the above-discussed deficiencies of ring oscillators, the present invention teaches a ring oscillator having the capability of minimizing the clock jitter and phase noise by eliminating the noise injection from the tail current to the oscillator and the kickback noise modulating tail current from the oscillator.
A low jitter CMOS ring oscillator circuit with a fully symmetrical differential current steering delay cell is described. This novel ring oscillator includes a first capacitor coupled between the first power supply rail and a bias voltage input for reducing the modulation of the tail current, such that the overall jitter or phase noise of the ring oscillator is minimized. At least one stage couples across this first capacitor. Each stage includes a first transistor, a second capacitor, and a fully symmetrical differential delay cell. In a first embodiment, the first transistor is a PMOS transistor, where the drain of the first PMOS transistor connects to the first power supply rail and the gate of the first PMOS transistor couple to the bias voltage input. The second capacitor couples between the source of the first transistor and ground and acts as a low pass filter. As a result, the second capacitor minimizes the effects of the thermal and flicker noise of the devices which provide the tail current. The fully symmetrical differential delay cell includes a control input, a differential input and a differential output. The control input couples to the source of the first PMOS transistor. When one stage is present, the differential input couples to the differential output. When more than one stage is present, the differential outputs couple to the differential inputs of the concurrent delay cell. In addition, the delay cell in the last stage couples to the differential input of the delay cell in the first stage.
In another embodiment, having similar configuration to the first embodiment, with the exceptions of (1) the first transistor is a NMOS transistor, where the drain of the first NMOS transistor connects to the ground and the gate of the first NMOS transistor couple to the bias voltage supply and (2) the first capacitor couples between the bias voltage supply and ground.
The focus of this new architecture is (1) to match the rising and falling output voltage in the delay cell, (2) to reduce the kickback noise from the oscillator to the tail current to minimize current modulation, and (3) to reduce the noise injection from the tail current to the oscillator. The rising and falling symmetry of the inverting delay cell output reduces the up-conversion of the low frequency noise, for example flicker noise.
The foregoing described ring oscillator""s primary application may be in clock generation for low-voltage handheld devices that require very low power and low jitter. An example of such may include hearing aid applications. It can also be used in circuits such as a PLL, DLL and other clock generator circuits that require low jitter and power.
Advantages of this design include but are not limited to a low power ring oscillator that exhibits minimal period jitter. This design consumes only one quarter of the current used in the conventional schemes, since the jitter of the ring oscillator is inversely proportional to the square root of the supply current. This is very important for low (micro) power applications. This design also may be integrated onto a chip, since low jitter can be achieved in this design using a low supply current. Thus, no external components are used, making the use of LC oscillators or crystal oscillators not necessary. This is very important for the applications with limited space such as hearing aid applications.